- New chip uses multiple nanotechnologies to reverse data bottleneck
- 3D architecture promises to address the communication “bottleneck”
- The architecture features interleaving layers of logic and memory
At a time when computer chips’ ability to process a glut of data is slowing, researchers, including one of Indian origin, have developed a three dimensional (3D) chip to tackle the situation.
Computers today comprise a chip for computing and another for data storage. As increased volumes of data are analysed, the limited rate at which data can be moved between the chips is creating a communication “bottleneck”.
The new prototype chip, detailed in the journal ‘Nature’, uses multiple nanotechnologies, together with a new 3D computer architecture, to reverse this trend.
“The new 3D computer architecture provides dense and fine-grained integration of computing and data storage, drastically overcoming the bottleneck from moving data between chips,” said Subhasish Mitra, Professor at Stanford University.
The researchers integrated over one million resistive random-access memory (RRAM) cells, a new type of memory storage, and two million carbon nanotube transistors for processing, making a dense 3D computer architecture with interleaving layers of logic and memory.
By inserting ultra-dense wires between these layers, the 3D architecture promises to address the communication “bottleneck”.
“Logic made from carbon nanotubes can be an order of magnitude more energy-efficient compared to today’s logic made from silicon and, similarly, RRAM can be denser, faster and more energy-efficient,” added Philip Wong from Stanford.
A big advantage to the find is that the new chip is compatible with today’s silicon infrastructure, both in terms of fabrication and design.
“The technology could not only improve traditional computing, but it also opens up a whole new range of applications that we can target,” said Max Shulaker, Assistant Professor at Massachusetts Institute of Technology.